Through-silicon via (TSV) is a 3D packaging technique that is developed to meet the needs of very large scale integration (VLSI) for integrated circuits. The TSV is expected to replace the traditional 2D interconnects. The TSV enables a chip stacking in three dimensions with higher density and smaller size by using 3D interconnect, such that the chip rate is significantly improved and the power consumption is reduced. Therefore, it is called the fourth generation packaging technology after wire bonding (WB), tape automated bonding (TAB) and flip chip (FC).
Generally, the process for creating a TSV structure of a wafer mainly includes the following steps.
(1) Preparation of though holes. Through-silicon vias with high width-to-depth ratio on the wafer are prepared by wet chemical etching (WCE), deep reactive-ion etching (DRIE) or laser drilling, etc.
(2) Electroplating of though holes. The metal of copper is electroplated through a pre-made metal seed layer to fill the entire through-silicon vias with the metal after a SiO2 insulating layer being prepared on sidewalls of the through-silicon vias.
(3) Chemical mechanical polishing (CMP). The wafer is thinned to expose the metal in the through-silicon vias by the polishing liquid and mechanical force.
In step (2), electroplating copper in the through holes is critically important to TSV technique so as to achieve electrical signal interconnect, which accounts for 40% of TSV cost.
At present, in step (2), a bottom-up electroplating is generally used for electroplating the copper in the through holes. The specific process is as follows. The wafer processed with a TSV structure and sputtered with a seed layer is immersed in an electroplating liquid including an accelerator, an inhibitor and a leveling agent, etc. The metal is deposited after the electroplating liquid enters the though holes to come into contact with the exposed seed layer. The copper is deposited along the though holes from bottom to top, gradually filling the through holes completely during the electroplating.
However, through-silicon vias of different sizes are generally processed on the same wafer according to the function requirements. During the electroplating process, the electroplating liquid are easy to enter the large vias due to its large size, so that the filling is fast; while the electroplating liquid is difficult to enter some through-silicon vias with extremely small size (with a diameter of 2-50 μm), resulting in slow electroplating filling. In addition, voids and gaps will also be formed, which seriously affect the reliability of the chip.
Similarly, for the printed circuit board, the above problems will also occur in the electroplating of the micro vias of different sizes that are provided on the same circuit board.
At present, there is still no method to achieve synchronous filling of vias with different sizes whether it is TSVs or the vias on the printed circuit board. Therefore, it is necessary to propose a method and a device to overcome the above defects, and realize the synchronous electroplating filling of the differential vias in one step.